The present invention relates to a semiconductor device and technology which is applicable to a power semiconductor device and a system using the same, for example.
In the large social movement of global environmental conservation, the importance of the electronics business which reduces an environmental burden is increasing. Especially, a power semiconductor device (also called a power device hereinafter) is employed in an inverter device of a railway vehicle, a hybrid vehicle, and an electric vehicle, in an inverter device of an air-conditioner, and in a power supply system of consumer devices such as a personal computer. The performance improvement of a power device contributes greatly to the power efficiency improvement of an infrastructure system or a consumer device. The power efficiency improvement means that energy resources necessary for operation of a system can be reduced; in other words, it means the reduction of a carbon dioxide emission, that is, the mitigation of the environmental burden. Accordingly, research and development aiming at the performance improvement of the power device are carried out actively in various companies.
A power device is often formed by employing silicon as a material, as is the case with an ordinary semiconductor integrated circuit (also called a device hereinafter). In a power conversion device (such as an inverter device) which uses a power device employing silicon (also called Si hereinafter) as a material, in order to reduce the energy loss generated in the inverter device, active development is performed for optimizing the element structure of a diode and a switching element and the profile of impurity concentration, thereby realizing a low on-resistance and a high current density. Moreover, as a material for power devices, a great attention has been directed in recent years toward a compound semiconductor such as silicon carbide (SiC) and gallium nitride (GaN) which are materials with a larger band gap than silicon (also called a wide band gap material hereinafter). The compound semiconductor has a large band gap and exhibits a destruction withstand voltage about 10 times higher than that of silicon. Accordingly, a compound semiconductor-based semiconductor device can make its film thickness thinner than a Si device and can reduce greatly the value of conduction resistance (Ron) of a switching element. Consequently, it is possible to reduce the so-called conduction loss (Ron×i×i), expressed by the product of resistance (Ron) and conduction current (i), contributing to the power efficiency improvement greatly. Paying attention to such a feature, development work of a diode and a switching element which utilize the compound semiconductor as a material is being actively conducted domestically and internationally.
When focusing on a switching device, commercialization of product is promoted quickly for a junction FET (called JFET hereinafter) as a compound semiconductor which employs SiC as the material. A JFET does not require an oxide film as compared with a MOSFET; therefore, there are few issues of the defect in the interface between the oxide film and the SiC and of the accompanying degradation of the element characteristic. Moreover, in a JFET, it is possible to control ON and OFF of the JFET by controlling the spread of a depletion layer formed in a PN junction; therefore, it is also easy to manufacture a normally-off element and a normally-on element separately. In this way, when compared with the MOSFET, the JFET has features that it is excellent in the long term reliability and is easy to manufacture as an element.
However, a normally-off JFET has the following issues. The gate region and source region of the JFET are semiconductor regions respectively having P-type conduction and N-type conduction, and have the so-called PN junction diode structure. Therefore, when the voltage between a gate and a source reaches about 3V, a parasitic diode between the gate and the source turns into an ON state. As a result, large current may flow between the gate and the source and the JFET may generate heat excessively, leading to breakdown. Accordingly, when the JFET is utilized as a normally-off switching element, it is desirable to utilize the JFET by limiting the voltage between the gate and the source to a low voltage of about 2.5V, and keeping the JFET in the state where the parasitic diode is not activated into an ON state or in the state where the diode current which flows between the gate and the source is sufficiently small.
In an ordinary MOSFET made from silicon, a normally-off MOSFET is set into an ON state, by the application of a gate voltage from 0V to about 15V or 20V. Accordingly, in order to utilize a normally-off JFET instead of a normally-off MOSFET, it is necessary to add to the existing gate driving circuit of a MOSFET, a step-down circuit (for example, a DC-DC converter) or a level conversion circuit, etc. which converts the gate voltage of about 15V or 20V into a voltage of about 2.5V. A design change and addition of components for that purpose will raise the cost of the whole system. In this way, although a JFET has features of being excellent in long term reliability and being easy to manufacture, the drive voltage of a gate is greatly different from that of a general MOSFET; therefore, there arises an issue that a large design change of a drive circuit becomes necessary, raising the cost of the whole system.
One of the methods of solving the present issue is a cascode connection method disclosed by Patent Literature 1. In the connection method, a normally-on JFET element and a MOSFET of a low withstand voltage are coupled in series. When coupled in this way, a drive circuit which drives a gate will drive the MOSFET; accordingly, it is not necessary to change the drive circuit. Furthermore, since it is series coupling, the withstand voltage between a drain and a source as both ends of the series coupling is determined by the characteristics of the JFET. Even when coupled in series, the on-resistance as a cascode element comprised of the series coupling of the JFET and the MOSFET is also suppressed comparatively small, because it is the series coupling of the low on-resistance of the JFET and the low on-resistance of the MOSFET of a low withstand voltage. In this way, the cascode connection method does not require the additional circuit (for example, the step-down circuit or the level conversion circuit described above) which is required when utilizing a normally-off JFET; accordingly it may be able to provide an easy-to-use switching element.
Patent Literature 2 discloses that in the cascode connection method, the gates of a JFET and a MOSFET are respectively driven by a drive circuit. In this method, an ON state voltage is applied to the MOSFET at the time of operation, and the MOSFET is set always in an ON state, as described in Rows 61 to 66 of Column 1 and Rows 30 to 40 of Column 4 of Patent Literature 2. In making it operate as a switching element of the cascode connection, 0V or a negative potential is applied to the gate of the JFET, thereby making it perform an ON and OFF operation. By such a control, it is possible to utilize the feature of the low on-resistance which the normally-on JFET has, and it is possible to reduce the conduction loss.    (Patent Literature 1) U.S. Pat. No. 4,663,547    (Patent Literature 2) U.S. Pat. No. 7,777,553    (Non Patent Literature 1) 2SK3069 Datasheet, dated on Sep. 7, 2005